1. Field of the Invention
The present invention relates to a data transfer circuit, and more particularly, it relates to a data transfer circuit transferring complementary data signals through two signal transfer lines.
2. Description of the Prior Art
In order to transfer a data signal in a semiconductor device, a method of changing the voltage of a signal transfer line is widely employed. For example, a data signal is transferred by changing the voltage of a single signal transfer line. In this method, however, the receiving end for the signal cannot determine the transferred data signal until a voltage amplitude exceeding a noise level is obtained, due to an influence by a noise superposed on the signal transfer line.
In a data transfer method for preventing this problem, two signal transfer lines DL01 and DL02 are arranged substantially in parallel with each other and a differential amplifier AMP01 is provided for comparing the potentials of the two signal transfer lines DL01 and DL02 with each other and amplifying the potential difference therebetween for determining the data signal, as shown in FIG. 26. This method can cancel influences, which are substantially identical to each other, by noises superposed on the two signal transfer lines DL01 and DL02.
Operations of this circuit are now described with reference to FIG. 27. Referring to FIG. 27, symbols Z1 and Z2 denote the voltages of the signal transfer lines DL01 and DL02 respectively.
Before data transfer, i.e., before a time t1, a precharge signal Pc is at a low level, and hence a precharge circuit PCG01 formed by three P-channel MOS transistors PT01, PT02 and PT03 operates to precharge the signal transfer lines DL01 and DL02 at a voltage Vdd. At this time, drivers DV1 and DV2 output high-level signals.
At a time t1, the precharge signal Pc goes high and the precharge circuit PCG01 is inactivated, thereby enabling data transfer.
At a time t2, either one of the drivers DV1 and DV2 outputs a low-level signal in response to the data to be transferred. It is assumed here that a signal S1 is at a high level and the driver DV1 outputs a low-level signal. While the voltage Z1 of the signal transfer line DL01 responsively starts to change from a high level to a low level, this change of the voltage Z1 is retarded as shown in FIG. 27 if the signal transfer line DL01 has a large length, due to the wiring capacitance and resistance of the signal transfer line DL01.
At a time t3, the potential difference between the voltages Z1 and Z2 reaches a level allowing the differential amplifier AMP01 to detect and amplify signals, and a control signal SE goes high to drive the differential amplifier AMP01.
When the data transfer is completed, the signal transfer lines DL01 and DL02 are precharged at the voltage Vdd again to prepare for next data transfer.
The precharge voltage, which is assumed to be Vdd in the above example, may be set at Vdd, Vss or 1/2Vcc in response to the usage for employing a data transmission circuit, a differential amplifier and a precharge circuit responsive to the voltage. In any case, the voltages of the two signal transfer lines DL01 and DL02 are equal to each other immediately before transferring the data, but different from each other after the data transfer. After completion of the data transfer, therefore, the two signal transfer lines DL01 and DL02 must be precharged at the same voltage for transmitting next data. Thus, the next data cannot be transmitted between a time t4 for starting the precharge operation and a time t5 when the potential Z1 of the signal transfer line DL01 completely reaches the precharge voltage Vdd.
If the signal transfer lines DL01 and DL02 have large lengths, the wiring resistances and capacitances thereof are increased to further increase the time required for precharging. Thus, the data transfer rate is disadvantageously reduced.